Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories

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http://doi.ieeecomputersociety.org/10.1109/MM.2005.64

July/August 2005 (vol. 25 no. 4) pp. 20-32

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	ASCII Text	x
	Yen-Jen Chang, Feipei Lai, "Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories," IEEE Micro, vol. 25, no. 4, pp. 20-32, July/August, 2005.

	BibTex	x
	@article{ 10.1109/MM.2005.64, author = {Yen-Jen Chang and Feipei Lai}, title = {Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories}, journal ={IEEE Micro}, volume = {25}, number = {4}, issn = {0272-1732}, year = {2005}, pages = {20-32}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.64}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories IS - 4 SN - 0272-1732 SP20 EP32 EPD - 20-32 A1 - Yen-Jen Chang, A1 - Feipei Lai, PY - 2005 KW - Cache KW - Dynamic zero-sensitivity KW - Bitlines KW - DZS KW - Power reduction VL - 25 JA - IEEE Micro ER -

Yen-Jen Chang, National Chung-Hsing University

Feipei Lai, National Taiwan University

A low-power cache has become essential in many applications, but cache accesses contribute significantly to a chip's total power consumption. Because most bit values read from the cache are 0s, the authors introduce a dynamic zero-sensitivity (DZS) scheme that reduces average cache power consumption by preventing bitlines from discharging in reading a 0.

Index Terms:

Cache, Dynamic zero-sensitivity, Bitlines, DZS, Power reduction

Citation:

Yen-Jen Chang, Feipei Lai, "Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories," IEEE Micro, vol. 25, no. 4, pp. 20-32, July/Aug. 2005, doi:10.1109/MM.2005.64

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