QsNetII: Defining High-Performance Network Design

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/MM.2005.75

July/August 2005 (vol. 25 no. 4) pp. 34-47

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Jon Beecroft Articles by David Addison Articles by David Hewson Articles by Moray McLaren Articles by Duncan Roweth Articles by Fabrizio Petrini Articles by Jarek Nieplocha

	ASCII Text	x
	Jon Beecroft, David Addison, David Hewson, Moray McLaren, Duncan Roweth, Fabrizio Petrini, Jarek Nieplocha, "QsNetII: Defining High-Performance Network Design," IEEE Micro, vol. 25, no. 4, pp. 34-47, July/August, 2005.

	BibTex	x
	@article{ 10.1109/MM.2005.75, author = {Jon Beecroft and David Addison and David Hewson and Moray McLaren and Duncan Roweth and Fabrizio Petrini and Jarek Nieplocha}, title = {QsNetII: Defining High-Performance Network Design}, journal ={IEEE Micro}, volume = {25}, number = {4}, issn = {0272-1732}, year = {2005}, pages = {34-47}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.75}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - QsNetII: Defining High-Performance Network Design IS - 4 SN - 0272-1732 SP34 EP47 EPD - 34-47 A1 - Jon Beecroft, A1 - David Addison, A1 - David Hewson, A1 - Moray McLaren, A1 - Duncan Roweth, A1 - Fabrizio Petrini, A1 - Jarek Nieplocha, PY - 2005 KW - Microprocessors and microcomputers KW - Network connectivity chips KW - Supercomputers KW - Clusters of Workstations KW - Communication Protocols VL - 25 JA - IEEE Micro ER -

Jon Beecroft, Quadrics

David Addison, Quadrics

David Hewson, Quadrics

Moray McLaren, Quadrics

Duncan Roweth, Quadrics

Fabrizio Petrini, Pacific Northwest National Laboratory

Jarek Nieplocha, Pacific Northwest National Laboratory

QsNetII optimizes interprocessor communication in systems built from standard server building blocks. Its short-message processing unit permits fast injection of small messages, providing ultra-low latency and scalability to thousands of nodes.

Index Terms:

Microprocessors and microcomputers, Network connectivity chips, Supercomputers, Clusters of Workstations, Communication Protocols

Citation:

Jon Beecroft, David Addison, David Hewson, Moray McLaren, Duncan Roweth, Fabrizio Petrini, Jarek Nieplocha, "QsNetII: Defining High-Performance Network Design," IEEE Micro, vol. 25, no. 4, pp. 34-47, July/Aug. 2005, doi:10.1109/MM.2005.75

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.