Formal Control Techniques for Power-Performance Management

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/MM.2005.87

September/October 2005 (vol. 25 no. 5) pp. 52-62

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Qiang Wu Articles by Philo Juang Articles by Margaret Martonosi Articles by Li-Shiuan Peh Articles by Douglas W. Clark

	ASCII Text	x
	Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark, "Formal Control Techniques for Power-Performance Management," IEEE Micro, vol. 25, no. 5, pp. 52-62, September/October, 2005.

	BibTex	x
	@article{ 10.1109/MM.2005.87, author = {Qiang Wu and Philo Juang and Margaret Martonosi and Li-Shiuan Peh and Douglas W. Clark}, title = {Formal Control Techniques for Power-Performance Management}, journal ={IEEE Micro}, volume = {25}, number = {5}, issn = {0272-1732}, year = {2005}, pages = {52-62}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.87}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Formal Control Techniques for Power-Performance Management IS - 5 SN - 0272-1732 SP52 EP62 EPD - 52-62 A1 - Qiang Wu, A1 - Philo Juang, A1 - Margaret Martonosi, A1 - Li-Shiuan Peh, A1 - Douglas W. Clark, PY - 2005 KW - Power performance management KW - dynamic voltage KW - frequency sealing KW - multiple-clock-domain KW - chip multiprocessors VL - 25 JA - IEEE Micro ER -

Qiang Wu, Princeton University

Philo Juang, Princeton University

Margaret Martonosi, Princeton University

Li-Shiuan Peh, Princeton University

Douglas W. Clark, Princeton University

These techniques determine when to speed up a processor to reach performance targets and when to slow it down to save energy. They use dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors.

Index Terms:

Power performance management, dynamic voltage, frequency sealing, multiple-clock-domain, chip multiprocessors

Citation:

Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark, "Formal Control Techniques for Power-Performance Management," IEEE Micro, vol. 25, no. 5, pp. 52-62, Sep./Oct. 2005, doi:10.1109/MM.2005.87

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.