Leakage Power Analysis and Reduction for Nanoscale Circuits

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http://doi.ieeecomputersociety.org/10.1109/MM.2006.39

March/April 2006 (vol. 26 no. 2) pp. 68-80

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	Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim, "Leakage Power Analysis and Reduction for Nanoscale Circuits," IEEE Micro, vol. 26, no. 2, pp. 68-80, March/April, 2006.

	BibTex	x
	@article{ 10.1109/MM.2006.39, author = {Amit Agarwal and Saibal Mukhopadhyay and Arijit Raychowdhury and Kaushik Roy and Chris H. Kim}, title = {Leakage Power Analysis and Reduction for Nanoscale Circuits}, journal ={IEEE Micro}, volume = {26}, number = {2}, issn = {0272-1732}, year = {2006}, pages = {68-80}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2006.39}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Leakage Power Analysis and Reduction for Nanoscale Circuits IS - 2 SN - 0272-1732 SP68 EP80 EPD - 68-80 A1 - Amit Agarwal, A1 - Saibal Mukhopadhyay, A1 - Arijit Raychowdhury, A1 - Kaushik Roy, A1 - Chris H. Kim, PY - 2006 KW - leakage power reduction KW - nanoscale circuits KW - CMOS KW - technology scaling VL - 26 JA - IEEE Micro ER -

Amit Agarwal, Intel Corp.

Saibal Mukhopadhyay, Purdue University

Arijit Raychowdhury, Purdue University

Kaushik Roy, Purdue University

Chris H. Kim, University of Minnesota

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.

Index Terms:

leakage power reduction, nanoscale circuits, CMOS, technology scaling

Citation:

Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim, "Leakage Power Analysis and Reduction for Nanoscale Circuits," IEEE Micro, vol. 26, no. 2, pp. 68-80, Mar./Apr. 2006, doi:10.1109/MM.2006.39

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