Robust On-Chip Communication

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http://doi.ieeecomputersociety.org/10.1109/MM.2006.63

May/June 2006 (vol. 26 no. 3) pp. 5

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	ASCII Text	x
	Pradip Bose, "Robust On-Chip Communication," IEEE Micro, vol. 26, no. 3, pp. 5, May/June, 2006.

	BibTex	x
	@article{ 10.1109/MM.2006.63, author = {Pradip Bose}, title = {Robust On-Chip Communication}, journal ={IEEE Micro}, volume = {26}, number = {3}, issn = {0272-1732}, year = {2006}, pages = {5}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2006.63}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Robust On-Chip Communication IS - 3 SN - 0272-1732 SP EP EPD - 5 A1 - Pradip Bose, PY - 2006 KW - high-performance computing KW - on-chip interconnects VL - 26 JA - IEEE Micro ER -

Pradip Bose, IBM T.J. Watson Research Center

The balance between computation and communication is a fundamental issue in application performance. As the chip industry gets entrenched in multicore architectures, this issue will become particularly and progressively important--not only in terms of chip-level performance, but also in terms of power, temperature, and reliability. Reliable communication is essential to overall computational robustness.

Index Terms:

high-performance computing, on-chip interconnects

Citation:

Pradip Bose, "Robust On-Chip Communication," IEEE Micro, vol. 26, no. 3, pp. 5, May/June 2006, doi:10.1109/MM.2006.63

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