The AMD Opteron Northbridge Architecture

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http://doi.ieeecomputersociety.org/10.1109/MM.2007.43

March/April 2007 (vol. 27 no. 2) pp. 10-21

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	Pat Conway, Bill Hughes, "The AMD Opteron Northbridge Architecture," IEEE Micro, vol. 27, no. 2, pp. 10-21, March/April, 2007.

	BibTex	x
	@article{ 10.1109/MM.2007.43, author = {Pat Conway and Bill Hughes}, title = {The AMD Opteron Northbridge Architecture}, journal ={IEEE Micro}, volume = {27}, number = {2}, issn = {0272-1732}, year = {2007}, pages = {10-21}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2007.43}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - The AMD Opteron Northbridge Architecture IS - 2 SN - 0272-1732 SP10 EP21 EPD - 10-21 A1 - Pat Conway, A1 - Bill Hughes, PY - 2007 KW - system topology KW - northbridge KW - microarchitecture KW - scalability KW - point-to-point networking VL - 27 JA - IEEE Micro ER -

Pat Conway, Advanced Micro Devices

Bill Hughes, Advanced Micro Devices

To increase performance while operating within a fixed power budget, the AMD Opteron processor integrates multiple x86-64 cores with a router and memory controller. AMD's experience with building a wide variety of system topologies using Opteron's HyperTransport-based processor interface has provided useful lessons that expose the challenges to be addressed when designing future system interconnect, memory hierarchy, and I/O to scale with both the number of cores and sockets in future x86-64 CMP architectures.

Index Terms:

system topology, northbridge, microarchitecture, scalability, point-to-point networking

Citation:

Pat Conway, Bill Hughes, "The AMD Opteron Northbridge Architecture," IEEE Micro, vol. 27, no. 2, pp. 10-21, Mar./Apr. 2007, doi:10.1109/MM.2007.43

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