Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The authors present experimental results from fully working 65-nm NoC designs and a detailed scalability analysis.
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Index Terms:
network on chip, deep submicron design, on-chip interconnection networks, design aids, low-power design, power management, multicore architectures
Citation:
Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini, "Bringing NoCs to 65 nm," IEEE Micro, vol. 27, no. 5, pp. 75-85, Sep./Oct. 2007, doi:10.1109/MM.2007.79
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