On-Chip Interconnection Architecture of the Tile Processor

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/MM.2007.89

September/October 2007 (vol. 27 no. 5) pp. 15-31

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by David Wentzlaff Articles by Patrick Griffin Articles by Henry Hoffmann Articles by Liewei Bao Articles by Bruce Edwards Articles by Carl Ramey Articles by Matthew Mattina Articles by Chyi-Chang Miao Articles by John F. Brown III Articles by Anant Agarwal

	ASCII Text	x
	David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal, "On-Chip Interconnection Architecture of the Tile Processor," IEEE Micro, vol. 27, no. 5, pp. 15-31, September/October, 2007.

	BibTex	x
	@article{ 10.1109/MM.2007.89, author = {David Wentzlaff and Patrick Griffin and Henry Hoffmann and Liewei Bao and Bruce Edwards and Carl Ramey and Matthew Mattina and Chyi-Chang Miao and John F. Brown III and Anant Agarwal}, title = {On-Chip Interconnection Architecture of the Tile Processor}, journal ={IEEE Micro}, volume = {27}, number = {5}, issn = {0272-1732}, year = {2007}, pages = {15-31}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2007.89}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - On-Chip Interconnection Architecture of the Tile Processor IS - 5 SN - 0272-1732 SP15 EP31 EPD - 15-31 A1 - David Wentzlaff, A1 - Patrick Griffin, A1 - Henry Hoffmann, A1 - Liewei Bao, A1 - Bruce Edwards, A1 - Carl Ramey, A1 - Matthew Mattina, A1 - Chyi-Chang Miao, A1 - John F. Brown III, A1 - Anant Agarwal, PY - 2007 KW - MIMD processors KW - on-chip interconnection networks KW - multicore architectures KW - mesh networks KW - parallel architectures VL - 27 JA - IEEE Micro ER -

David Wentzlaff, Tilera

Patrick Griffin, Tilera

Henry Hoffmann, Tilera

Liewei Bao, Tilera

Bruce Edwards, Tilera

Carl Ramey, Tilera

Matthew Mattina, Tilera

Chyi-Chang Miao, Tilera

John F. Brown III, Tilera

Anant Agarwal, Tilera

iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use. Taking advantage of the five networks, the c-based iLib interconnection library efficiently maps program communication across the on-chip interconnect. The Tile Processor's first implementation, the TILE64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.

[1] 15 M.B. Taylor et al., "Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams," Proc. Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 2-13.
[2] E. Waingold et al., "Baring It All to Software: Raw Machines," Computer, vol. 30, no. 9, Sept. 1997, pp. 86-93.
[3] M.B. Taylor et al., "Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 341-353.
[4] MPI: A Message-Passing Interface Standard, Message Passing Interface Forum, 1994; http://www.mpi-forum.org/docs/mpi-11-html mpi-report.html.
[5] J.M. Lebak, Polymorphous Computing Architectures (PCA) Example Application 4: Corner-Turn, tech. report, MIT Lincoln Laboratory, 2001.

Index Terms:

MIMD processors, on-chip interconnection networks, multicore architectures, mesh networks, parallel architectures

Citation:

David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal, "On-Chip Interconnection Architecture of the Tile Processor," IEEE Micro, vol. 27, no. 5, pp. 15-31, Sep./Oct. 2007, doi:10.1109/MM.2007.89

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.