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A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs
San Jose, California, USA August 09-August 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2004.1Records of the 2004 International Wor ...
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Saman Adham, Benoit Nadeau-Dostie, "A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 98-101, Records of the 2004 International Workshop on Memory Technology, Design and Testing (MTDT'04), 2004.
 
 
BibTex
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@article{ 10.1109/MTDT.2004.1,
author = {Saman Adham and Benoit Nadeau-Dostie},
title = {A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs},
journal ={Memory Technology, Design and Testin, IEEE International Workshop on},
volume = {0},
year = {2004},
issn = {1087-4852},
pages = {98-101},
doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2004.1},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Memory Technology, Design and Testin, IEEE International Workshop on
TI - A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs
SN - 1087-4852
SP98
EP101
A1 - Saman Adham,
A1 - Benoit Nadeau-Dostie,
PY - 2004
KW - null
VL - 0
JA - Memory Technology, Design and Testin, IEEE International Workshop on
ER -
 
Saman Adham, LogicVision, Inc.
Benoit Nadeau-Dostie, LogicVision, Inc.
The use of group (or bit) write enable in memories is becoming very common in embedded memories. The circuitry used to achieve these functions need be thoroughly tested for different kind of defects using specific test sequence. However, most BIST algorithms assume that these write enables are forced active during the global write cycle in the BIST run. This paper presents a serial interface BIST algorithm that is used to test defect on bit/group write enables of these memories.
Citation:
Saman Adham, Benoit Nadeau-Dostie, "A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs," mtdt, pp.98-101, Records of the 2004 International Workshop on Memory Technology, Design and Testing (MTDT'04), 2004
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