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Functional Test Selection for High Volume Manufacturing
Austin, Texas December 04-December 05
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTV.2006.12Seventh International Workshop on Mic ...
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Vijay Gangaram, Intel Corporation, USA
Deepa Bhan, Intel Corporation, USA
James K. Caldwell, Intel Corporation, USA
Validation and legacy test suites are often reused for achieving at speed coverage required for testing high frequency semiconductor chips. Porting validation tests to high volume manufacturing (HVM) flows involves extensive manual effort but is required to ensure high quality chips. Functional test selection is the problem of choosing a subset of tests from a large pool of existing tests to maximize the fault coverage while minimizing the test data volume, fault grading time and porting effort. We formulate a framework for test selection that allows various coverage metrics to be used for evaluation. A novel dynamic untestability analysis method is proposed to identify faults that can not be detected by a given test sequence. Conversely this method can be used to compute tight upper bound coverage and hence as a metric for functional test evaluation. Test selection using this new metric gives significant additional fault coverage than toggle based test selection.
Index Terms:
Functional Test Sequences, Design Validation, Test Sequence Compaction, Fault Simulation Acceleration, Untestable Fault Identification
Citation:
Vijay Gangaram, Deepa Bhan, James K. Caldwell, "Functional Test Selection for High Volume Manufacturing," mtv, pp.15-19, Seventh International Workshop on Microprocessor Test and Verification (MTV'06), 2006
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