On-chip debug is an important technique to detect and locate the faults in the practical software applications. Scalability and reusability are the essential features of System-on- Chip (SoC). Therefore, the debug architecture should meet the requirement of those features. Furthermore, it is necessary for applications developers to communication with the SoC chip on-line. In this paper, we present the novel debug architecture to solve above problems. The debug architecture has been implemented in a typical SoC chip. The results of performance analysis show that the debug architecture has high performance at the cost of few resources and area.