As we enter the era of many-core processors and complex SoCs, on-chip interconnection networks play a dominant role in determining the performance, power, and cost of a system. These networks are critically dependent on a number of underlying technologies: channel, buffer, and switch circuits, router microarchitecture, flow-control and routing methods, and network topology. Too often on-chip networks are built in a naive manner using a ring or mesh topology and standard cell methodology. Compared to this approach, optimized circuits can reduce power by an order of magnitude and an optimized topology can give an additional factor of two to three in area and power efficiency. This talk will explore key enabling technologies for on-chip networks giving a number of examples and identifying opportunities for future research.