NoC Design and Implementation in 65nm Technology

Princeton, New Jersey May 07-May 09

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http://doi.ieeecomputersociety.org/10.1109/NOCS.2007.30

First International Symposium on Netw ...

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	Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini, "NoC Design and Implementation in 65nm Technology," Networks-on-Chip, International Symposium on, pp. 273-282, First International Symposium on Networks-on-Chip (NOCS'07), 2007.

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	@article{ 10.1109/NOCS.2007.30, author = {Antonio Pullini and Federico Angiolini and Paolo Meloni and David Atienza and Srinivasan Murali and Luigi Raffo and Giovanni De Micheli and Luca Benini}, title = {NoC Design and Implementation in 65nm Technology}, journal ={Networks-on-Chip, International Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2773-6}, pages = {273-282}, doi = {http://doi.ieeecomputersociety.org/10.1109/NOCS.2007.30}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Networks-on-Chip, International Symposium on TI - NoC Design and Implementation in 65nm Technology SN - 0-7695-2773-6 SP273 EP282 A1 - Antonio Pullini, A1 - Federico Angiolini, A1 - Paolo Meloni, A1 - David Atienza, A1 - Srinivasan Murali, A1 - Luigi Raffo, A1 - Giovanni De Micheli, A1 - Luca Benini, PY - 2007 KW - null VL - 0 JA - Networks-on-Chip, International Symposium on ER -

Antonio Pullini, Politecnico di Torino, Italy

Federico Angiolini, University of Bologna, Italy

Paolo Meloni, University of Cagliari, Italy

David Atienza, LSI, EPFL, Switzerland; Complutense University, Spain

Srinivasan Murali, Stanford University, California, USA

Luigi Raffo, University of Cagliari, Italy

Giovanni De Micheli, LSI, EPFL, Switzerland

Luca Benini, University of Bologna, Italy

As embedded computing evolves towards ever more pow- erful architectures, the challenge of properly interconnect- ing large numbers of on-chip computation blocks is becom- ing prominent. Networks-on-Chip (NoCs) have been pro- posed as a scalable solution to both physical design issues and increasing bandwidth demands. However, this claim has not been fully validated yet, since the design properties and tradeoffs of NoCs have not been studied in detail below the 100 nm threshold.

This work is aimed at shedding light on the opportunities and challenges, both expected and unexpected, of NoC de- sign in nanometer CMOS. We present fully working 65 nm NoC designs, a complete NoC synthesis flow and detailed scalability analysis.

Citation:

Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini, "NoC Design and Implementation in 65nm Technology," nocs, pp.273-282, First International Symposium on Networks-on-Chip (NOCS'07), 2007

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