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A Power and Energy Exploration of Network-on-Chip Architectures
Princeton, New Jersey May 07-May 09
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NOCS.2007.6First International Symposium on Netw ...
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Arnab Banerjee, University of Cambridge, UK
Robert Mullins, University of Cambridge, UK
Simon Moore, University of Cambridge, UK
In this study, we analyse the move towards Networks-on- Chips from an energy perspective by accurately modelling a Circuit-Switched router, a Wormhole router and a speculative Virtual-Channel router in a 90nm CMOS process. All the routers are shown to dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data-path. This leads to the key result that, if this trend continues, the energy cost of more elaborate control will not be vast, making it easier to justify. Given effective clock-gating, this additional energy is also shown to be more or less independent of network congestion. Accurate speed and area metrics are also reported for the networks, which will allow a more complete comparison to be made across the NoC architectural space considered.
Citation:
Arnab Banerjee, Robert Mullins, Simon Moore, "A Power and Energy Exploration of Network-on-Chip Architectures," nocs, pp.163-172, First International Symposium on Networks-on-Chip (NOCS'07), 2007
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