ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

April 07-April 10

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http://doi.ieeecomputersociety.org/10.1109/NOCS.2008.13

Second ACM/IEEE International Symposi ...

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	Mikkel Bystrup Stensgaard, Jens Spars?, "ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology," Networks-on-Chip, International Symposium on, pp. 55-64, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008.

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	@article{ 10.1109/NOCS.2008.13, author = {Mikkel Bystrup Stensgaard and Jens Spars?}, title = {ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology}, journal ={Networks-on-Chip, International Symposium on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3098-7}, pages = {55-64}, doi = {http://doi.ieeecomputersociety.org/10.1109/NOCS.2008.13}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Networks-on-Chip, International Symposium on TI - ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology SN - 978-0-7695-3098-7 SP55 EP64 A1 - Mikkel Bystrup Stensgaard, A1 - Jens Spars?, PY - 2008 KW - Network-on-Chip KW - Reconfigurable KW - Communication KW - Application-specific KW - System-on-Chip KW - VL - 0 JA - Networks-on-Chip, International Symposium on ER -

Mikkel Bystrup Stensgaard

Jens Spars?

This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit-switching as found in FPGAs. The paper presents the ReNoC (ReconfigurableNoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology

Index Terms:

Network-on-Chip, Reconfigurable, Communication, Application-specific, System-on-Chip,

Citation:

Mikkel Bystrup Stensgaard, Jens Spars?, "ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology," nocs, pp.55-64, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008

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