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Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
April 07-April 10
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NOCS.2008.17Second ACM/IEEE International Symposi ...
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A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.
Index Terms:
Real-Time Performance, System on Chip, Network on Chip, Cyclo-Static Dataflow
Citation:
Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij, "Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip," nocs, pp.211-212, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008
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