In this paper we propose a design-driven iterative partitioning algorithm for Verilog based on module instances instead of gates. We do this in order to take advantage of the design hierarchy information contained in the modules and their instances. A Verilog instance represents one vertex in the circuit hypergraph. The vertex can be flattened into multiple vertices in the event that a load balance is not achieved by instance based partitioning. In this case the algorithm flattens the largest instance and moves gates between the partitions in order to improve the load balance.

Our experiments show that this partitioning algorithm produces a smaller cutsize than is produced by hmetis on a gate-level netlist. It produces better speedup for the simulation because it takes advantage of the design hierarchy.