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Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations
Bialystok, Poland September 13-September 17
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.18International Symposium on Parallel C ...
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Alexander A. Petrovsky, Sergei L. Shkredov, "Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations," Parallel Computing in Electrical Engineering, International Conference on, pp. 181-186, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006.
 
 
BibTex
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@article{ 10.1109/PARELEC.2006.18,
author = {Alexander A. Petrovsky and Sergei L. Shkredov},
title = {Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2006},
isbn = {0-7695-2554-7},
pages = {181-186},
doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.18},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations
SN - 0-7695-2554-7
SP181
EP186
A1 - Alexander A. Petrovsky,
A1 - Sergei L. Shkredov,
PY - 2006
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Alexander A. Petrovsky, Bialystok Technical University, Poland
Sergei L. Shkredov, Belarusian State University of Informatics and Radioelectronics, Russia
The results presented in the article are based on a methodology for automatic synthesis of real-time split radix 2-4 parallel-pipeline FFT-processors at structural level. The approach is oriented at reconfigurable FPGAaware design and allows taking into account real-time application restrictions (input data structure and format, operating frequency, transform size, overall throughput) as well as other design restrictions (CLB-count, area, power dissipation). The considered design examples prove method's good abilities for hardware optimization. Variants of split radix 2-4 computing element implementation are compared. Switching over from floating point arithmetics to fixed point data and the corresponding accuracy issues are considered.
Citation:
Alexander A. Petrovsky, Sergei L. Shkredov, "Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations," parelec, pp.181-186, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006
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