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Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors
Bialystok, Poland September 13-September 17
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.36International Symposium on Parallel C ...
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Bj?rn Griese, Boris Kettelhoit, Mario Porrmann, "Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors," Parallel Computing in Electrical Engineering, International Conference on, pp. 214-219, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006.
 
 
BibTex
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@article{ 10.1109/PARELEC.2006.36,
author = {Bj?rn Griese and Boris Kettelhoit and Mario Porrmann},
title = {Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2006},
isbn = {0-7695-2554-7},
pages = {214-219},
doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.36},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors
SN - 0-7695-2554-7
SP214
EP219
A1 - Bj?rn Griese,
A1 - Boris Kettelhoit,
A1 - Mario Porrmann,
PY - 2006
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Bj?rn Griese, University of Paderborn, Germany
Boris Kettelhoit, University of Paderborn, Germany
Mario Porrmann, University of Paderborn, Germany
Dynamically reconfigurable FPGAs are well known to combine the flexibility of software with the performance of application specific hardware. As such they can be used as powerful but still flexible coprocessors in embedded processor systems. In this paper we analyze different variants for interfacing reconfigurable hardware from an embedded processor. We describe three different on-chip busses and evaluate their usability for dynamically reconfigurable systems. In addition, we analyze the communication latencies and the speed-up factor of a hardware accelerator for floating point operations for a total of eight different coupling variants.
Citation:
Bj?rn Griese, Boris Kettelhoit, Mario Porrmann, "Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors," parelec, pp.214-219, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006
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