This document presents the concept of integrating the SHECS (Shared Explicit Cache System)-based critical sections with SMP scheduler to obtain the efficient general purpose hardware mutual exclusion facility in the TLP-CMP (Thread-Level Parallelism - Chip Multiprocessing) SMP (Symmetric Multiprocessing) architectures. There are presented two solutions - the first integrates the SHECS-based CS with Software Multi- Queue SMP Scheduler, the second integrates the SHECSbased CS with Hardware Multi-Queue SMP Scheduler implemented as an additional functional unit within the TLP-CMP. The both propositions are implemented and simulated with using SoC (System-on-Chip) such as Intel? IXP 2800 network processor. The results of proveof- concept simulation (obtained with the IXA SDK 4.2 Workbench simulation environment) are presented and discussed in this document.