A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering

Taipei, Taiwan December 04-December 07

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http://doi.ieeecomputersociety.org/10.1109/PDCAT.2006.7

Seventh International Conference on P ...

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	Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin, "A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering," Parallel and Distributed Computing Applications and Technologies, International Conference on, pp. 44-49, Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06), 2006.

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	@article{ 10.1109/PDCAT.2006.7, author = {Tze-Yun Sung and Yaw-Shih Shieh and Chun-Wang Yu and Hsi-Chin Hsin}, title = {A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering}, journal ={Parallel and Distributed Computing Applications and Technologies, International Conference on}, volume = {0}, year = {2006}, isbn = {0-7695-2736-1}, pages = {44-49}, doi = {http://doi.ieeecomputersociety.org/10.1109/PDCAT.2006.7}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

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	TY - CONF JO - Parallel and Distributed Computing Applications and Technologies, International Conference on TI - A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering SN - 0-7695-2736-1 SP44 EP49 A1 - Tze-Yun Sung, A1 - Yaw-Shih Shieh, A1 - Chun-Wang Yu, A1 - Hsi-Chin Hsin, PY - 2006 KW - Redundant CORDIC arithmetic KW - CORDIC algorithm KW - 3-D vector interpolation KW - high-throughput. VL - 0 JA - Parallel and Distributed Computing Applications and Technologies, International Conference on ER -

Tze-Yun Sung, Chung Hua University, Taiwan

Yaw-Shih Shieh, Chung Hua University, Taiwan

Chun-Wang Yu, Chung Hua University, Taiwan

Hsi-Chin Hsin, National Formosa University, Taiwan

High performance architectures can be designed for data intensive and latency tolerant applications by maximizing the parallelism and pipelining of the algorithm. The hardware primitives for 3-D rotation for high throughput 3-D vector interpolation are presented in this paper. The primitives are based on the CORDIC algorithm. The proposed architecture of the 3-D vector interpolator using redundant CORDIC arithmetic is presented in this paper. The highthroughput 3-D vector interpolator is implemented by VLSI.

Index Terms:

Redundant CORDIC arithmetic, CORDIC algorithm, 3-D vector interpolation, high-throughput.

Citation:

Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin, "A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering," pdcat, pp.44-49, Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06), 2006

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