Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications

Taipei, Taiwan December 04-December 07

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/PDCAT.2006.72

Seventh International Conference on P ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Zheng Liang Articles by Juha Plosila Articles by Lu Yan Articles by Kaisa Sere

	ASCII Text	x
	Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere, "Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications," Parallel and Distributed Computing Applications and Technologies, International Conference on, pp. 344-347, Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06), 2006.

	BibTex	x
	@article{ 10.1109/PDCAT.2006.72, author = {Zheng Liang and Juha Plosila and Lu Yan and Kaisa Sere}, title = {Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications}, journal ={Parallel and Distributed Computing Applications and Technologies, International Conference on}, volume = {0}, year = {2006}, isbn = {0-7695-2736-1}, pages = {344-347}, doi = {http://doi.ieeecomputersociety.org/10.1109/PDCAT.2006.72}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel and Distributed Computing Applications and Technologies, International Conference on TI - Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications SN - 0-7695-2736-1 SP344 EP347 A1 - Zheng Liang, A1 - Juha Plosila, A1 - Lu Yan, A1 - Kaisa Sere, PY - 2006 KW - null VL - 0 JA - Parallel and Distributed Computing Applications and Technologies, International Conference on ER -

Zheng Liang, Turku Centre for Computer Science (TUCS), Finland

Juha Plosila, University of Turku, Finland

Lu Yan, Abo Akademi University, Finland

Kaisa Sere, Abo Akademi University, Finland

This paper presents an advanced self-timed Java accelerator core which has extremely low power consumption while providing sufficient performance for even the most demanding real-time telecommunication and multimedia applications. The goal is that the accelerator can be directly attached to any general-purpose processor core running some Java-intensive application software. Asynchronous self-timed circuit technology, where timing is based on local handshakes between circuit blocks instead of a global clock signal, provides a promising platform for obtaining a highly modular low-power Java accelerator implementation.

Citation:

Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere, "Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications," pdcat, pp.344-347, Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06), 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.