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A Novel Fault Tolerant Approach for SRAM-Based FPGAs
Hong Kong, China December 16-December 17
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.1999.816210Sixth Pacific Rim International Sympo ...
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Jian Xu, Fudan University
Paifa Si, Fudan University
Weikang Huang, Fudan University
Fabrizio Lombardi, Texas A&M University
This paper presents a novel fault tolerant approach for SRAM-Based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. Fault tolerant routing procedure under this novel approach is simple and less time-consuming. We provide the simulation results and show that the proposed approach has lower overhead than previous methods found in technical literature[1, 4].
Index Terms:
FPGA, fault-tolerant routing, fault-tolerant architecture
Citation:
Jian Xu, Paifa Si, Weikang Huang, Fabrizio Lombardi, "A Novel Fault Tolerant Approach for SRAM-Based FPGAs," prdc, pp.40, Sixth Pacific Rim International Symposium on Dependable Computing (PRDC'99), 1999
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