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Hardware Fault Tolerance in Arithmetic Coding for Data Compression
Hong Kong, China December 16-December 17
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PRDC.1999.816214Sixth Pacific Rim International Sympo ...
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G. Robert Redinbo, University of California at Davis
New fault tolerance techniques are presented for protecting a lossless compression algorithm, arithmetic coding, whose recursive nature makes it vulnerable to temporary hardware failures. The fundamental arithmetic operations are protected by low-cost residue codes, employing fault tolerance in multiplications and additions. Additional fault-tolerant design techniques are developed to protect other critical steps such as normalization and rounding, bit stuffing and index selection. For example, the decoding step that selects the next symbol is checked by comparing local values with estimates already calculated in other parts of the decoding structure. Bit stuffing, a procedure for limiting very long carry propagations, is checked through modified residue values, whereas normalization and rounding after multiplication are protected by efficiently modifying the multiplier to produce residue segments.
Index Terms:
Fault-tolerant data compression, residue codes, arithmetic coding, fault-tolerant rounding, protected normalization
Citation:
G. Robert Redinbo, "Hardware Fault Tolerance in Arithmetic Coding for Data Compression," prdc, pp.70, Sixth Pacific Rim International Symposium on Dependable Computing (PRDC'99), 1999
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