Design of Defect Tolerant Wallace Multiplier

Changsha, Hunan, China December 12-December 14

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http://doi.ieeecomputersociety.org/10.1109/PRDC.2005.30

11th Pacific Rim International Sympos ...

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	Kazuteru NAMBA, Hideo IT0, "Design of Defect Tolerant Wallace Multiplier," Pacific Rim International Symposium on Dependable Computing, IEEE, pp. 300-304, 11th Pacific Rim International Symposium on Dependable Computing (PRDC'05), 2005.

	BibTex	x
	@article{ 10.1109/PRDC.2005.30, author = {Kazuteru NAMBA and Hideo IT0}, title = {Design of Defect Tolerant Wallace Multiplier}, journal ={Pacific Rim International Symposium on Dependable Computing, IEEE}, volume = {0}, year = {2005}, isbn = {0-7695-2492-3}, pages = {300-304}, doi = {http://doi.ieeecomputersociety.org/10.1109/PRDC.2005.30}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Pacific Rim International Symposium on Dependable Computing, IEEE TI - Design of Defect Tolerant Wallace Multiplier SN - 0-7695-2492-3 SP300 EP304 A1 - Kazuteru NAMBA, A1 - Hideo IT0, PY - 2005 KW - null VL - 0 JA - Pacific Rim International Symposium on Dependable Computing, IEEE ER -

Kazuteru NAMBA, Chiba University, Japan

Hideo IT0, Chiba University, Japan

This paper proposes a design of a defect tolerant Wallace multipliers. A repair procedure for the pro- posed design i s also shown. T h i s paper evaluates t h e proposed design from the view point of t h e yield, area and delay time. For example, the yield of a 32 x 32 Wallace multiplier increases from 0.90 t o 0.99 by applying the proposed design while the area increases by a factor of 1.39.

Citation:

Kazuteru NAMBA, Hideo IT0, "Design of Defect Tolerant Wallace Multiplier," prdc, pp.300-304, 11th Pacific Rim International Symposium on Dependable Computing (PRDC'05), 2005

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