This paper reports our experience on the development of a design-for-safety (DFS) workbench called Risk Assessment and Management Environment (RAME) for microelectronic avionics systems. RAME is built upon an information infrastructure that comprises a test-reporting/failure-tracking system, an off-the-shelf data mining tool, a knowledge base, and a fault model. This infrastructure permits systematic learning from prior projects and enables the automation of failure mode, effect and criticality analysis (FMECA). More importantly, RAME is able to directly accept source code in hardware description languages (HDLs) for automated design validation.