Over the past few years, there has been an increasing interest in using partial and run-time reconfigurable (RTR) FPGAs to develop reconfigurable systems for various applications. To support this new type of hardware, new or improved design methodologies and tools are needed that can provide sufficient support for RTR-related design and verification tasks. This paper first introduces a novel concept called Run-Time Reconfigurable Co-Emulation, which extends traditional co-emulation with the RTR capability of FPGAs. It then describes and discusses how to develop hardware platforms that use the RTR co-emulation concept for transaction-level functional verification and in-circuit debugging of RTR-based FPGA designs.