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Hardware/Firmware Verification of Graphic IP
Porto Alegre, RS, Brazil May 28-May 30
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/RSP.2007.2518th IEEE/IFIP International Workshop ...
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Kamdem Romain, "Hardware/Firmware Verification of Graphic IP," Rapid System Prototyping, IEEE International Workshop on, pp. 48-56, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), 2007.
 
 
BibTex
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@article{ 10.1109/RSP.2007.25,
author = {Kamdem Romain},
title = {Hardware/Firmware Verification of Graphic IP},
journal ={Rapid System Prototyping, IEEE International Workshop on},
volume = {0},
year = {2007},
issn = {1074-6005},
pages = {48-56},
doi = {http://doi.ieeecomputersociety.org/10.1109/RSP.2007.25},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Rapid System Prototyping, IEEE International Workshop on
TI - Hardware/Firmware Verification of Graphic IP
SN - 1074-6005
SP48
EP56
A1 - Kamdem Romain,
PY - 2007
KW - null
VL - 0
JA - Rapid System Prototyping, IEEE International Workshop on
ER -
 
Kamdem Romain, STMicroelectronics

This paper describes methods and simulation techniques used to verify the functional correctness of a Flexible Video Processing Engine IP1.

The verification environment relies on co-simulation of the RTL IP under-design with Functional Building Blocks2, developed using SystemC constructs. We try here to assess a number of problems encountered during the verification of complex IPs such as flexibility of functions, simulation speed and performance.

Citation:
Kamdem Romain, "Hardware/Firmware Verification of Graphic IP," rsp, pp.48-56, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), 2007
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