In this paper, a HW CABAC encoder architecture is proposed targeting H.264/AVC main profile. CABAC and Rate Distortion Optimization (RDO) are two important coding tools that enhance coding efficiency of H.264/AVC. However, coding speed of CABAC encoder is limited by the coding data dependence and its serial coding procedure, and RDO requires large memory resource and costs long delay of memory access to backup and restore CABAC context state data. The CABAC encoder of this paper utilizes pipeline structure at top level to reduce data dependence, and coding speed of one symbol per cycle is achieved. A context managing mechanism is designed that fully supports RDO coding of H.264/AVC encoder. It significantly reduces context memory cost and operation delay for context backup and restore. 85% of context memory resource is reduced comparing to the reference design. Synthesis result shows that the encoder can work at 620 MHz targeting 0.13um CMOS process.