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A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation
Porto Alegre, RS, Brazil May 28-May 30
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/RSP.2007.618th IEEE/IFIP International Workshop ...
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Fernando Kronbauer, Alexandro Baldassin, Bruno Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo, "A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation," Rapid System Prototyping, IEEE International Workshop on, pp. 123-129, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), 2007.
 
 
BibTex
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@article{ 10.1109/RSP.2007.6,
author = {Fernando Kronbauer and Alexandro Baldassin and Bruno Albertini and Paulo Centoducatte and Sandro Rigo and Guido Araujo and Rodolfo Azevedo},
title = {A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation},
journal ={Rapid System Prototyping, IEEE International Workshop on},
volume = {0},
year = {2007},
issn = {1074-6005},
pages = {123-129},
doi = {http://doi.ieeecomputersociety.org/10.1109/RSP.2007.6},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Rapid System Prototyping, IEEE International Workshop on
TI - A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation
SN - 1074-6005
SP123
EP129
A1 - Fernando Kronbauer,
A1 - Alexandro Baldassin,
A1 - Bruno Albertini,
A1 - Paulo Centoducatte,
A1 - Sandro Rigo,
A1 - Guido Araujo,
A1 - Rodolfo Azevedo,
PY - 2007
KW - null
VL - 0
JA - Rapid System Prototyping, IEEE International Workshop on
ER -
 
Fernando Kronbauer, State University of Campinas, Brazil
Alexandro Baldassin, State University of Campinas, Brazil
Bruno Albertini, State University of Campinas, Brazil
Paulo Centoducatte, State University of Campinas, Brazil
Sandro Rigo, State University of Campinas, Brazil
Guido Araujo, State University of Campinas, Brazil
Rodolfo Azevedo, State University of Campinas, Brazil
Transactional memory (TM) is an emerging synchronization mechanism that aims to solve most of the difficulties inherent in lock-based approaches. TM implementations may either rely on special hardware (HTM) or employ a software-only (STM) technique. While STM can be implemented and evaluated in current machines, HTM requires hardware modification and a prototyping infrastructure. We present in this paper a flexible platform framework for rapid prototyping and evaluation of HTM systems. Platform components such as cache, memory and interconnection medium are implemented using SystemC and Transaction-Level Modeling (TLM). Processors are described in an Architecture Description Language (ADL) which makes it practical to change the Instruction Set Architecture (ISA), since simulators and binary utilities are automatically generated by the ADL toolset. The resulting flexibility allows designers to explore the design space in a simple and uniform manner. We illustrate the platform through a case study based on the original HTM proposed by Herlihy and Moss. Simulation results are shown for microbenchmarks supporting up to 256 processors.
Citation:
Fernando Kronbauer, Alexandro Baldassin, Bruno Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo, "A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation," rsp, pp.123-129, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), 2007
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