The integration phase of real-time COTS-based systems is often problematic because when multiple tasks run con- currently, the interference at the bus level between cache fetching activities and I/O peripheral transactions is signif- icant and causes unpredictable behaviors: experimentally, tasks can have computation time variance up to 50%. In this work, we present a theoretical framework able to model the interaction between CPU and peripherals contending for shared main memory through the Front Side Bus (FSB). We first show how to compute worst case execution times for a task given a trace of its cache activity and given an up- per bound function that models peripheral activities; then, we introduce the novel idea of "hardware server" as a means of controlling the unpredictable behavior of COTS periph- eral components.