Embedded system designers tend to use small and simple cache memories. This kind of caches can experience poor performance because of their not flexible placement policy. In this scenario, a big fraction of the misses can originate from the mismatch between the cache behavior and the memory accesses' locality features. A way to increase the performance is to modify the program layout to fit the cache structure. This strategy needs the solution of a N-P complete problem and very long processing time to determine the optimum layout. We propose an object level transformation technique to look for a program layout that minimizes the number of misses by means of smart heuristics. The solution transforms the program layout using the standard functionalities of a linker. Using some standard benchmarks and several embedded applications, we show the benefits of transforming program layout on various cache configurations.