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Software Verification and Validation within the (Rational) Unified Process
Greenbelt, Maryland December 03-December 04
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/SEW.2003.127074628th Annual NASA Goddard Software Eng ...
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Christopher Fuhrman, ?cole de technologie sup?rieure, Montreal, Canada
Fatime Djlive, ?cole de technologie sup?rieure, Montreal, Canada
Edgardo Palza, ?cole de technologie sup?rieure, Montreal, Canada
We discuss the integration of software verification and validation activities (as defined by the IEEE Std. 1012) within the Unified Process. We compare and contrast these two process frameworks, and identify the aspects of verification and validation that are directly supported, partially supported or not supported by the Unified Process.
Citation:
Christopher Fuhrman, Fatime Djlive, Edgardo Palza, "Software Verification and Validation within the (Rational) Unified Process," sew, pp.216, 28th Annual NASA Goddard Software Engineering Workshop (SEW'03), 2003
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