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Formal Verification of Abstract System and Protocol Specifications
Columbia, Maryland April 24-April 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/SEW.2006.1930th Annual IEEE/NASA Software Engine ...
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Axel Schneider, Lucent Technologies Network Systems GmbH, Nurnberg
Thomas Bluhm, Lucent Technologies Network Systems GmbH, Nurnberg
Tobias Renner, Lucent Technologies Network Systems GmbH, Nurnberg
Ulrich Heinkel, Lucent Technologies Network Systems GmbH, Nurnberg
Joachim Knablein, Lucent Technologies Network Systems GmbH, Nurnberg
Reynaldo Zavala, Lucent Technologies Network Systems GmbH, Nurnberg
Formal methods such as automated model checking are used commercially for digital circuit design verification. These techniques find errors early in the product cycle, which improves development time and cost. By contrast, the current practice in complex system design is to specify system functions and protocol details in natural language. Some errors are found early by manual inspections, but others are only revealed during implementation testing or by costly field failures. We describe our application of formal specification and model checking to real telecom product development, and enumerate the classes of specification errors that these formal techniques revealed at an early stage of the development cycle.
Citation:
Axel Schneider, Thomas Bluhm, Tobias Renner, Ulrich Heinkel, Joachim Knablein, Reynaldo Zavala, "Formal Verification of Abstract System and Protocol Specifications," sew, pp.207-211, 30th Annual IEEE/NASA Software Engineering Workshop SEW-30 (SEW'06), 2006
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