High Performance Dense Ring Generators
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This paper presents an enhanced architecture of on-chip pseudorandom test pattern generators, test data decompressors, and test response compactors based on ring generators. The new structure is aimed at improving layout and routing properties while, at the same time, reducing propagation delays introduced by associated phase shifters.
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Index Terms:
Index Terms- Built-in self-test, design for testability, linear feedback shift registers, phase shifters, ring generators.
Citation:
Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, "High Performance Dense Ring Generators," IEEE Transactions on Computers, vol. 55, no. 1, pp. 83-87, Jan. 2006, doi:10.1109/TC.2006.11
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