Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs
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The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive different channels at different data rates. Examples of such ATEs include the Agilent 93000 series tester based on port scalability and the test processor-per-pin architecture and the Tiger system from Teradyne. The number of tester channels with high data rates may be constrained in practice, however, due to ATE resource limitations, the power rating of the SOC, and scan frequency limits for the embedded cores. Therefore, we formulate the following optimization problem: Given two available data rates for the tester channels, an SOC-level test access mechanism (TAM) width W, an upper limit V (V < W) on the number of channels that can transport test data at the higher data rate, determine an SOC TAM architecture that minimizes the testing time. We present an efficient heuristic algorithm for TAM optimization that exploits port scalability of ATEs to reduce SOC testing time and test cost. We present experimental results for the ITC '02 SOC test benchmarks and investigate the impact of dual-speed TAM architectures on power consumption during testing for one of these benchmarks.
[1] 120 Verigy, “Agilent 93000 Flexible Parallel Test Solution,” http://www.verigy.com/content/dav/verigy/ Internet/Products/V93000%20SOC%20Series 5989-2598EN.pdf, 2006.
[2] A. Khoche, Agilent Corp., private communication, 2004.
[3] Teradyne Tech nologies, “Tiger: Advanced Digital with Silicon Germanium Technology,” http://www.teradyne.com/tigerdigital.html , 2006.
[4] P. Harrod, “Testing Reusable IP—A Case Study,” Proc. IEEE Int'l Test Conf. (ITC), pp. 493-498, Sept. 1999.
[5] E.J. Marinissen et al., “A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores,” Proc. IEEE Int'l Test Conf. (ITC), pp. 284-293, 1998.
[6] P. Varma and S. Bhatia, “A Structured Test Re-Use Methodology for Core-Based System Chips,” Proc. IEEE Int'l Test Conf. (ITC), pp.294-302, 1998.
[7] S.K. Goel and E.J. Marinissen, “Effective and Efficient Test Architecture Design for SOCs,” Proc. IEEE Int'l Test Conf. (ITC), pp. 529-538, 2002.
[8] E. Larsson and H. Fujiwara, “Power Constrained Preemptive TAM Scheduling,” Proc. IEEE European Test Workshop (ETW), pp.119-126, May 2002.
[9] M. Nourani and J. Chin, “Test Scheduling with Power-Time Tradeoff and Hot-Spot Avoidance Using MILP,” Proc. IEE Computers and Digital Techniques, pp. 341-355, 2004.
[10] P. Rosinger, B. Al-Hashimi, and N. Nicolici, “Power Constrained Test Scheduling Using Power Profile Manipulation,” Proc. Int'l Symp. Circuits and Systems (ISCAS), vol. V, pp. 251-254, May 2001.
[11] D. Zhao and S. Upadhyay, “Power Constrained Test Scheduling with Dynamically Varied TAM,” Proc. VLSI Test Symp., pp. 273-278, 2003.
[12] V. Immaneni and S. Raman, “Direct Access Test Scheme—Design of Block and Core Cells for Embedded ASICs,” Proc. IEEE Int'l Test Conf. (ITC), pp. 488-492, Sept. 1990.
[13] I. Ghosh, N.K. Jha, and S. Dey, “A Low Overhead Design for Testability and Test Generation Technique for Core-Based Systems,” Proc. IEEE Int'l Test Conf. (ITC), pp. 50-59, Nov. 1997.
[14] I. Ghosh, S. Dey, and N.K. Jha, “A Fast and Low Cost Testing Technique for Core-Based System-on-Chip,” Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 542-547, June 1998.
[15] N. Touba and B. Pouya, “Testing Embedded Cores Using Partial Isolation Rings,” Proc. IEEE VLSI Test Symp. (VTS), pp. 10-16, Apr. 1997.
[16] Y. Huang et al., “Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm,” Proc. IEEE Int'l Test Conf. (ITC), pp. 74-82, 2002.
[17] V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization,” Proc. IEEE VLSI Test Symp. (VTS), pp. 253-258, 2002.
[18] E. Larsson and Z. Peng, “An Integrated System-on-Chip Test Framework,” Proc. Design, Automation, and Test in Europe (DATE) Conf., pp. 138-144, 2001.
[19] E. Larsson and Z. Peng, “An Integrated Framework for the Design and Optimization of SOC Test Solutions,” J. Electronic Testing: Theory and Applications, vol. 18, pp. 385-400, 2002.
[20] A. Sehgal, V. Iyengar, and K. Chakrabarty, “SOC Test Planning Using Virtual Test Access Architectures,” IEEE Trans. VLSI Systems, vol. 12, pp. 1196-1202, Dec. 2004.
[21] Q. Xu and N. Nicolici, “Time/Area Tradeoffs in Testing Hierarchical SOCs with Hard Megacores,” Proc. IEEE Int'l Test Conf., pp. 1196-1202, 2004.
[22] V. Iyengar, K. Chakrabarty, and E.J. Marinissen, “Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores,” J. Electronic Testing: Theory and Applications, vol. 18, no. 2, pp. 213-230, Apr. 2002.
[23] K. Chakrabarty, “Optimal Test Access Architectures for System-on-a-Chip,” ACM Trans. Design Automation of Electronic Systems, vol. 6, pp. 26-49, Jan. 2001.
[24] E.J. Marinissen, V. Iyengar, and K. Chakrabarty, “A Set of Benchmarks for Modular Testing of SOCs,” Proc. IEEE Int'l Test Conf. (ITC), pp. 519-528, 2002, http://www.extra.research. philips.comitc02socbenchm /.
[25] Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch, “Test Power: A Big Issue in Large SOC Designs,” Proc. DELTA Workshop, pp. 447-449, 2002.
[26] N. Nicolici and B.M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits. Kluwer Academic, 2003.
[27] M.S. Hsiao, E.M. Rudnick, and J.H. Patel, “Effects of Delay Models on Peak Power Estimation of VLSI Sequential Circuits,” Proc. Int'l Conf. Computer-Aided Design (ICCAD), pp. 45-51, 1997.
[28] R. Burch, F. Najm, P. Yang, and T. Trick, “A Monte Carlo Approach for Power Estimation,” IEEE Trans. VLSI Systems, vol. 1, pp. 63-71, Mar. 1993.
[29] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” Proc. IEEE VLSI Test Symp. (VTS), pp. 6-11, Apr. 1993.
[30] A. Sehgal and K. Chakrabarty, “Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures,” Proc. Design, Automation and Test in Europe (DATE), pp. 422-427, 2004.
Index Terms:
Full-chip testing, SOC testing, test scheduling, test access mechanism, dual-speed TAM, TAM optimization.
Citation:
Anuja Sehgal, Krishnendu Chakrabarty, "Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs," IEEE Transactions on Computers, vol. 56, no. 1, pp. 120-133, Jan. 2007, doi:10.1109/TC.2007.15
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