Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
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This paper presents a detailed analysis of the behavior of a novel, fault-tolerant, 32-bit embedded CPU when compared to a default (non fault-tolerant) implementation of the same processor, during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, probability of fault manifestation and the behavior of latent faults.
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Index Terms:
fault injection, fault modeling and simulation, SEU, soft error, microprocessor test, fault tolerance
Citation:
Emmanuel Touloupis, James A. Flint, Vassilios A. Chouliaras, David D. Ward, "Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor," IEEE Transactions on Computers, vol. 56, no. 12, pp. 1585-1596, June 2007, doi:10.1109/TC.2007.70766
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