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A 256Meg SDRAM BIST for Disturb Test Application
Washington D.C. November 01-November 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TEST.1997.639614International Test Conference 1997 (I ...
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Theo J. Powell, Francis Hii, Dan Cline, "A 256Meg SDRAM BIST for Disturb Test Application," Test Conference, International, pp. 200, International Test Conference 1997 (ITC'97), 1997.
 
 
BibTex
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@article{ 10.1109/TEST.1997.639614,
author = {Theo J. Powell and Francis Hii and Dan Cline},
title = {A 256Meg SDRAM BIST for Disturb Test Application},
journal ={Test Conference, International},
volume = {0},
year = {1997},
issn = {1089-3539},
pages = {200},
doi = {http://doi.ieeecomputersociety.org/10.1109/TEST.1997.639614},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - A 256Meg SDRAM BIST for Disturb Test Application
SN - 1089-3539
SP
EP
A1 - Theo J. Powell,
A1 - Francis Hii,
A1 - Dan Cline,
PY - 1997
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Theo J. Powell, Texas Instruments, Inc.
Francis Hii, Texas Instruments Singapore, PTE. LTD.
Dan Cline, Texas Instruments, Inc.
The Disturb Test Algorithms are targeted for row adjacent coupled defects that can be time elapsed dependent. A BIST design is described for application of these tests for testing 256Meg SDRAM chips.
Citation:
Theo J. Powell, Francis Hii, Dan Cline, "A 256Meg SDRAM BIST for Disturb Test Application," itc, pp.200, International Test Conference 1997 (ITC'97), 1997
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