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Low Power Hardware Architecture for VBSME Using Pixel Truncation
Hyderabad, India January 04-January 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.10021st International Conference on VLSI ...
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Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan, "Low Power Hardware Architecture for VBSME Using Pixel Truncation," VLSI Design, International Conference on, pp. 389-395, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.
 
 
BibTex
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@article{ 10.1109/VLSI.2008.100,
author = {Asral Bahari and Tughrul Arslan and Ahmet T. Erdogan},
title = {Low Power Hardware Architecture for VBSME Using Pixel Truncation},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2008},
issn = {1063-9667},
pages = {389-395},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.100},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Low Power Hardware Architecture for VBSME Using Pixel Truncation
SN - 1063-9667
SP389
EP395
A1 - Asral Bahari,
A1 - Tughrul Arslan,
A1 - Ahmet T. Erdogan,
PY - 2008
VL - 0
JA - VLSI Design, International Conference on
ER -
 
This paper presents an efficient architecture to imple- ment low power variable block size motion estima- tion (VBSME) using full search. Power reduction is achieved by performing the search in two steps: low pixel resolution and full pixel resolution. We analysed the computation and memory units needed to support these two search modes. The proposed architecture re- duces the total energy consumption by 50% with 6% additional area compared to the conventional architec- ture.
Citation:
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan, "Low Power Hardware Architecture for VBSME Using Pixel Truncation," vlsid, pp.389-395, 21st International Conference on VLSI Design (VLSI Design 2008), 2008
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