designing single error correcting Galois field multipliers over polynomial basis. The proposed method uses multiple parity prediction circuits to detect and correct logic errors and gives 100% fault coverage both in the functional unit and the parity prediction circuitry. Area, power and delay overhead for the proposed design technique is analyzed. It is found that compared to the traditional Triple Modular Redundancy (TMR) techniques for single error correction the proposed technique is very cost efficient. Index Terms: Error Correcting Codes, Galois Field Multiplier, Cryptography, VLSI.