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Integrated TIA-Equalizer for High Speed Optical Link
Hyderabad, India January 04-January 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.3121st International Conference on VLSI ...
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Saurav Bandyopadhyay, Pradip Mandal, Stephen E. Ralph, Kenneth Pedrotti, "Integrated TIA-Equalizer for High Speed Optical Link," VLSI Design, International Conference on, pp. 208-213, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.
 
 
BibTex
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@article{ 10.1109/VLSI.2008.31,
author = {Saurav Bandyopadhyay and Pradip Mandal and Stephen E. Ralph and Kenneth Pedrotti},
title = {Integrated TIA-Equalizer for High Speed Optical Link},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2008},
issn = {1063-9667},
pages = {208-213},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.31},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Design, International Conference on
TI - Integrated TIA-Equalizer for High Speed Optical Link
SN - 1063-9667
SP208
EP213
A1 - Saurav Bandyopadhyay,
A1 - Pradip Mandal,
A1 - Stephen E. Ralph,
A1 - Kenneth Pedrotti,
PY - 2008
VL - 0
JA - VLSI Design, International Conference on
ER -
 
This paper introduces an integrated TIA (Transimpedance Amplifier) Equalizer combination for a low cost Giga-Bit Optical Communication System with perfluorinated Graded Index Plastic Optic Fiber (GI-POF) offering a large optical bandwidth. To realize the potential cost advantages offered by POF based data link, a large area photodiode is used to reduce costly alignment precision, with a TIA- equalizer. Equalization is needed due to bandwidth limitation resulting from the large photodiode. The Photo-Detector capacitance with input impedance of the TIA forms a dominant low frequency pole. Equalizer extends the bandwidth of the whole system by introducing a peak in its frequency response at high frequencies to compensate the loss of bandwidth. The main focus is to use an inexpensive, large area Photo- Detector to increase fiber to detector alignment tolerance simultaneously preserving system speed using the equalizer. This system is for a bit rate varying from 1 to 3Gbps. The TIA-Equalizer combination was implemented with 0.18m Digital CMOS process using 1.8V Supply.
Citation:
Saurav Bandyopadhyay, Pradip Mandal, Stephen E. Ralph, Kenneth Pedrotti, "Integrated TIA-Equalizer for High Speed Optical Link," vlsid, pp.208-213, 21st International Conference on VLSI Design (VLSI Design 2008), 2008
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