Power consumption, physical size, and architecture de- sign of sensor node processors have been the focus of sen- sor network research in the architecture community. What lies at the foundation for these research is the hardware- level design which determines the boundaries for achievable utility and performance. Architecture design and evaluation, however, cannot be accomplished independent of the appli- cations and software that run on these sensor nodes. On one hand, some researchers have proposed architectures that can cater to a variety of application classes while trading off on some performance improvements. On the other hand, a set of application-specific architectures have been proposed which perform certain operations extremely well but are not versa- tile enough to run a variety of applications. This paper provides a design space exploration and op- timizations platform to characterize the processor and ISA design tailored for a particular application or a class of ap- plications. We collect a wide variety of sensor network ap- plications to create a comprehensive benchmark suite called the WiSeNBench. We then present a careful profiling of these benchmark applications using an ARM simulator to identify some of the key characteristic behaviors. This also opens up avenue for a possible re-look at the classes of applications that could be supported on next-generation sensor networks and efficient architectural designs to enable these applica- tions.