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A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores
Hyderabad, India January 04-January 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.7521st International Conference on VLSI ...
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Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron, "A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores," VLSI Design, International Conference on, pp. 273-278, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.
 
 
BibTex
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@article{ 10.1109/VLSI.2008.75,
author = {Rajaraman Ramanarayanan and Sanu Mathew and Vasantha Erraguntla and Ram Krishnamurthy and Shay Gueron},
title = {A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2008},
issn = {1063-9667},
pages = {273-278},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.75},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores
SN - 1063-9667
SP273
EP278
A1 - Rajaraman Ramanarayanan,
A1 - Sanu Mathew,
A1 - Vasantha Erraguntla,
A1 - Ram Krishnamurthy,
A1 - Shay Gueron,
PY - 2008
VL - 0
JA - VLSI Design, International Conference on
ER -
 
This paper describes a unified PopCount/ BitScanForward/BitScanReverse datapath circuit designed for 2.1GHz operation with total power consumption of 6.5mW, targeted for 65nm 64-bit microprocessor execution cores. The unified datapath uses a hybrid 3:2 compressor-based Wallace tree to count the number of `1's in the 64-bit input, along with a novel encoding scheme that enables reuse of the same tree to identify the bit-location of the 1st set bit when scanning the input in the forward and reverse directions. This circuit thus combines the functions of 3 separate units, enabling 26% reduction in total energy and 20% lower area, while achieving single-cycle latency & throughput.
Citation:
Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron, "A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores," vlsid, pp.273-278, 21st International Conference on VLSI Design (VLSI Design 2008), 2008
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