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Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm
Hyderabad, India January 04-January 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.8221st International Conference on VLSI ...
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Monjur Alam, Santosh Ghosh, Dipanwita RoyChowdhury, Indranil Sengupta, "Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm," VLSI Design, International Conference on, pp. 693-698, 21st International Conference on VLSI Design (VLSI Design 2008), 2008.
 
 
BibTex
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@article{ 10.1109/VLSI.2008.82,
author = {Monjur Alam and Santosh Ghosh and Dipanwita RoyChowdhury and Indranil Sengupta},
title = {Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2008},
issn = {1063-9667},
pages = {693-698},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.82},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm
SN - 1063-9667
SP693
EP698
A1 - Monjur Alam,
A1 - Santosh Ghosh,
A1 - Dipanwita RoyChowdhury,
A1 - Indranil Sengupta,
PY - 2008
VL - 0
JA - VLSI Design, International Conference on
ER -
 
tor/decryptor core implementation of Advanced Encryption Stan- dard (AES-Rijndael) cryptosystem. The suggested architecture is capable of handling all possible combinations of standard bit lengths (128,192,256) of data and key. The fully rolled inner- pipelined architecture ensures lesser hardware complexity. The architecture does reutilize precomputed blocks, in the sense that the same hardware is shared during encryption and decryption as much as possible. The design has been implemented on Xilinx XCVe1000-8bg560 device. The performance of the architecture has been compared with existing results in the literature and has been found to be the most efficient (throughput/area) implemen- tation of the AES algorithm. Index Terms--Reconfigurable Architecture, AES, Rijndael, S- box, Composite fields.
Citation:
Monjur Alam, Santosh Ghosh, Dipanwita RoyChowdhury, Indranil Sengupta, "Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm," vlsid, pp.693-698, 21st International Conference on VLSI Design (VLSI Design 2008), 2008
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