In this paper we present an iterative binding algorithm for high-level synthesis design space exploration, that simultaneously optimizes clock period and wirelength. Our algorithm uses a stochastic interconnect distribution model and a top-down partition-based global placement in a novel framework to provide fast and accurate estimates for wire length and wire delays during resource binding in high-level synthesis. The wirelength estimates used in our algorithm are within 15% of wirelengths in layouts created by commercial and academic placement tools. Experiments show that when compared to a clique- partitioning based binding technique, the proposed algorithm improves the clock period by an average of 18%, with minimal impact on the total wirelength. In addition, our algorithm is an order-of-magnitude faster than a traditional synthesis technique that uses a full place-and-route as part of the design space exploration process.