On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder

Hyderabad, India January 03-January 07

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http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.124

19th International Conference on VLSI ...

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	ASCII Text	x
	K. Maharatna, A. Troya, M. Krstic, E. Grass, "On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder," VLSI Design, International Conference on, pp. 613-618, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.

	BibTex	x
	@article{ 10.1109/VLSID.2006.124, author = {K. Maharatna and A. Troya and M. Krstic and E. Grass}, title = {On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2006}, issn = {1063-9667}, pages = {613-618}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.124}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder SN - 1063-9667 SP613 EP618 A1 - K. Maharatna, A1 - A. Troya, A1 - M. Krstic, A1 - E. Grass, PY - 2006 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

K. Maharatna, University of Bristol

A. Troya, Infineon Technology

M. Krstic, IHP

E. Grass, IHP

This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have been used to reduce the power consumption and the inherent bandwidth mismatch between the Add-Compare-Select (ACS) and traceback operations. Aggressive clock gating and innovative circuit techniques reduce the power consumption further. The normalized cell area and dynamic power consumption of the designed VD are 5.9 mm² and 53 mW respectively. The normalized power dissipation of the VD is 0.66 mW/Mbps.

Citation:

K. Maharatna, A. Troya, M. Krstic, E. Grass, "On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder," vlsid, pp.613-618, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

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