A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18? Digital CMOS

Hyderabad, India January 03-January 07

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http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.13

19th International Conference on VLSI ...

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	Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya, "A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18? Digital CMOS," VLSI Design, International Conference on, pp. 69-74, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.

	BibTex	x
	@article{ 10.1109/VLSID.2006.13, author = {Subhadeep Banik and Daibashish Gangopadhyay and T. K. Bhattacharyya}, title = {A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18? Digital CMOS}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2006}, issn = {1063-9667}, pages = {69-74}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.13}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18? Digital CMOS SN - 1063-9667 SP69 EP74 A1 - Subhadeep Banik, A1 - Daibashish Gangopadhyay, A1 - T. K. Bhattacharyya, PY - 2006 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Subhadeep Banik, Indian Institute of Technology - Kharagpur

Daibashish Gangopadhyay, Indian Institute of Technology - Kharagpur

T. K. Bhattacharyya, Indian Institute of Technology - Kharagpur

This paper is devoted to the design and implementation of high speed, low power, low voltage flash analog-to-digital convertors (ADC). A 4-bit flash ADC, with a maximum acquisition speed of 400 MHz, is implemented in a 1.8 V analog supply voltage. The large input signal dynamic range is handled using a fast switching common mode jump circuit, implemented with complementary pass transistors, which eliminates the need for high input-common-mode-range (ICMR) preamplifier based comparators. The measured INL/DNL is 0.4/1.1 LSB. The Signal-to-noise-plus-distortion ratio (SNDR) obtained at 12.5 MHz input is 21.25 dB. The spurious-free dynamic range (SFDR) is 27.6 dB and power consumption is only 30 mW. Design and simulations results are presented in dual-poly 0.18? pure digital CMOS technology.

Citation:

Subhadeep Banik, Daibashish Gangopadhyay, T. K. Bhattacharyya, "A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18? Digital CMOS," vlsid, pp.69-74, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

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