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Phase Change Memory Faults
Hyderabad, India January 03-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.13419th International Conference on VLSI ...
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M. Jagadesh Kumar, Ali A. Orouji, "Phase Change Memory Faults," VLSI Design, International Conference on, pp. 108-112, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
 
 
BibTex
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@article{ 10.1109/VLSID.2006.134,
author = {M. Jagadesh Kumar and Ali A. Orouji},
title = {Phase Change Memory Faults},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2006},
issn = {1063-9667},
pages = {108-112},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.134},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Phase Change Memory Faults
SN - 1063-9667
SP108
EP112
A1 - M. Jagadesh Kumar,
A1 - Ali A. Orouji,
PY - 2006
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
M. Jagadesh Kumar, Indian Institute of Technology - New Delhi
Ali A. Orouji, Semnan University
Using two-dimensional simulation, we report a new Gate-induced Barrier Field Effect Transistor (GBFET) which exhibits at least three orders of magnitude less OFF state leakage current when compared to a conventional poly-Si TFT. We demonstrate that the GBFET is completely free of pseudo-subthreshold conduction making it a very attractive device for active matrix liquid crystal display systems.
Citation:
M. Jagadesh Kumar, Ali A. Orouji, "Phase Change Memory Faults," vlsid, pp.108-112, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
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