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Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design
Hyderabad, India January 03-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.15219th International Conference on VLSI ...
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Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak, "Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design," VLSI Design, International Conference on, pp. 606-612, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
 
 
BibTex
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@article{ 10.1109/VLSID.2006.152,
author = {Maryam Ashouei and Abhijit Chatterjee and Adit D. Singh and Vivek De and T. M. Mak},
title = {Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2006},
issn = {1063-9667},
pages = {606-612},
doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.152},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design
SN - 1063-9667
SP606
EP612
A1 - Maryam Ashouei,
A1 - Abhijit Chatterjee,
A1 - Adit D. Singh,
A1 - Vivek De,
A1 - T. M. Mak,
PY - 2006
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Maryam Ashouei, Georgia Institute of Technology
Abhijit Chatterjee, Georgia Institute of Technology
Adit D. Singh, Auburn University
Vivek De, Intel Corporation
T. M. Mak, Intel Corporation
Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. It has been shown that the layout of a circuit can significantly affect the variation in leakage power by controlling the effect of spatially correlated across- die process variations. In this paper, a method, which efficiently estimates the distribution of leakage power variation caused by correlated process variations, is proposed. The accuracy of the method was validated by comparing the estimated leakage power distribution with Monte Carlo simulation results on ISCAS benchmark circuits. Furthermore, it is shown how the method can be used as a guideline to determine the best possible layout of a circuit.
Citation:
Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak, "Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design," vlsid, pp.606-612, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
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