Ruchir Puri, Tanay Karnik, Rajiv Joshi,
"Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies,"
VLSI Design, International Conference on, pp. 5-7, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
BibTex
x
@article{
10.1109/VLSID.2006.156, author = {Ruchir Puri and Tanay Karnik and Rajiv Joshi}, title = {Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2006}, issn = {1063-9667}, pages = {5-7}, doi = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.156}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - CONF JO - VLSI Design, International Conference on TI - Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies SN - 1063-9667 SP5 EP7 A1 - Ruchir Puri, A1 - Tanay Karnik, A1 - Rajiv Joshi, PY - 2006 KW - null VL - 0 JA - VLSI Design, International Conference on ER -
Ruchir Puri, Tanay Karnik, Rajiv Joshi, "Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies," vlsid, pp.5-7, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006
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